Transistor Architecture Simulator

Benchmarking 1-Bit Single Transistor Ops vs. 2-Bit Paired Transistor (Base-4 Dibit) Execution

Ready to run benchmark.
Paired Transistor (Base-4) Efficiency Advantage
0.00x

Combined CPU throughput and Memory Bus bandwidth gain

CPU Logic Processing

Instruction evaluation & bit manipulation speed

1-Bit Sequential (Base-2) 1 Bit/Tick
Execution Time: 0 ms
Compute Speed: 0 MOp/s
2-Bit Paired (Base-4) 2 Bits/Tick (Dibit)
Execution Time: 0 ms
Compute Speed: 0 MOp/s

Memory Bandwidth & Bus Efficiency

Simulated memory transfer & state decoding

Base-2 Bus Transfer Serial Bit Lines
Transfer Time: 0 ms
Bandwidth: 0 MB/s
Base-4 Paired Bus Transfer Dibit Bus Lines
Transfer Time: 0 ms
Bandwidth: 0 MB/s

Architectural Breakdown

Metric 1-Bit Transistor Logic (Base 2) 2-Bit Paired Transistors (Base 4) Theoretical Gain
State Representation per Unit 2 States (0, 1) 4 States (00, 01, 10, 11) 2.00x Info Density / Unit
Cycles per 8-bit Byte 8 Clock Cycles 4 Clock Cycles 50% Reduction in Cycle Overhead
Bus Control Overhead High (8 strobe pulses/byte) Low (4 strobe pulses/byte) 2.00x Control Efficiency